This invention relates to serial data transfer circuits, such as shift registers. In particular, the invention is intended for use in an active matrix liquid crystal display system for reducing the power consumption.
There is at present an urgent need for planar type display devices, such as active matrix liquid crystal display panels. Similar to the conventional types of CRT displays, the column electrodes of the matrix must be successively driven for the transfer of video signal data at a very high frequency, of the order of 4 MHz. Due to the very large number of column electrodes, considerable amount of power is consumed in charging and discharging the input capacitance of the shift registers driving the column electrodes.
FIG. 1 is a general circuit diagram of a column electrode drive circuit for a liquid crystal display device. In this figure, F1, F2, . . . , Fm are delay flip-flops connected in series to form a shift-register. In response to a clock signal .phi., the input video signal data D is sequentially shifted into the shift register and outputted to the different column electrodes Y1, Y2 . . . , Ym. In FIG. 2, waveform (a) shows a video signal of one horizontal line between two synchronization pulses; waveform (b) are set signals; waveform (c) shows the clock pulses; waveforms Y1, Y2, Y3, Y4 are column signals from the different flip-flops in FIG. 1. As shown in these waveforms, Y1, Y2, Y3, Y4 are non-overlapping timing signals to feed sequentially the different column electrodes of the liquid crystals.
In FIG. 1, a set of series-connected shift register stages 20 constitute the column electrode drive circuit, with a clock signal being continuously applied to shift register 20. In this case, it is necessary to provide 640 shift register stages in order to sequentially select 640 column electrodes, while each selection signal pulse must have a peak voltage of the order of 10 volts. It is necessary for the clock signal to charge and discharge all the node capacitance at a frequency of the order of 4 MHz. Since the power dissipation is equal to the product of total capacitance, frequency and the square of the peak voltage, a substantial amount of power is consumed.
A method to overcome this dissipation problem was proposed in Japanese Patent Laid-Open Publication No. 56-4184. The proposed method is shown in FIG. 3. The shift register stages constituting the column electrode drive circuits are divided into a number of groups. As shown in FIG. 3, there are k groups and each group has a shift register with flip-flops such as F1, F2, . . . , F.sub.n with corresponding outputs Q1 to Qn in the first group of shift registers and F.sub.n+1 in subsequent groups of shift registers. These outputs are used to control the switches which connect the video signal to the different column electrodes. Terminal D is the input for the set signal for timing data as shown in FIG. 2. Terminal .phi. is the input terminal for the timing signal for the logic gates G1, G2, . . . , Gk to control the different groups of flip-flops. There are k number of logic gates, indicated as G1, G2, . . . , Gk. These gates are for the shift register to generate clock pulses for selectively turning on different groups of flip-flops. Thus, the shift register 37 is divided into k blocks, and only the neighboring columns are turned on by the clock pulses from the shift register. It is no longer necessary to turn on all the flip-flops in the shift register. The clock control block 10 forms a second shift register, which has output data at terminal C1, C2, . . . to sequentialy turn on one of the gates G1, G2, . . . , Gk. Block 10 is a frequency divider to divide the set clock pulse by a ratio of 1/n.
If there are m number of flip-flops in the column drive shift register 37 divided into k groups, each group has n number of flip-flops which consume power. If f is the frequency at the clock input terminal .phi. and c is the node capacitance of every flip flop, a conventional circuit would consume a power p=fcmV.sup.2. With the grouping method, the power becomes p.sub.1 =fcnV.sup.2. Thus, by increasing the number of grouping k, the power consumption can be reduced.
The foregoing method, however, has the following disadvantages: Firstly, the operation is not stable. With reference to FIG. 4, it is assumed that the selection signal pulse Qn from the final stage Fn of the first group of shift register stages is to result in the initiation of a succeeding selection signal pulse for the first stage of the next group flip-flops Fn+1 at a time t1. That is to say, prior to time t1, the second group of shift register stages is to be selected to receive the clock signal, while after t1 the second group of shift register stages is to be selected. The corresponding clock control circuit 10 generates waveforms C1 and C2 as shown in FIG. 4, and the corresponding clock signals supplied to the first and second groups of column drive shift registers are designated as .phi.1 and .phi.2 respectively. However, as is clear from FIG. 4, signal .phi.2 does not undergo a level transition for data write-in of the selection signal Qn to shift register stage Fn+1 at time t1.
In this case, no column electrode selection pulse is outputted from column drive shift register stage Fn+1. In order to achieve a transfer of the selection signal from stage Fn to stage Fn+1 at this instant, it is necessary for the control signal pulses C1 and C2 to overlap during time t1. However, if this is done, a pulse in the form of a spike as indicated in waveform .phi.2' is produced at time t1, and served as a clock signal pulse to the second group of column drive shift register stages Fn+1, Fn+2, . . . etc. This spike may false trigger the F.sub.n+1 flip-flop to produce a selection signal pulse of the form Q'.sub.n+1 shown in FIG. 4. Such pulses are not produced in a consistent manner, and the data transfer between the groups of shift register stages is extremely unreliable.